Integrated circuits are tested for manufacturing defects by applying a set of stimuli, called test vectors to the circuits. These test patterns can be applied from an external piece of Automatic Test Equipment (ATE), or they can be generated internally through use of Built-In Self-Test (BIST). Externally applied test patterns may be created by an Automatic Test Pattern Generation (ATPG) tool. The BIST is an on-chip tester that creates a set of test patterns corresponding to signals that will be generated on-chip for analysis of fault coverage and for verification.
ATPG and BIST tools also create a set of expected responses (output patterns) of the circuit under the test (CUT) as a function of the input stimuli. Typically, circuit models and libraries used by ATPG and BIST tools for generating the expected patterns are different from those used in designing the circuit. The ATE or on-chip hardware use the expected patterns to check that the CUT is performing correctly. Thus, if the expected responses are incorrect, every IC fabricated will fail the verification test by the BIST or ATE even if the IC operates correctly. Therefore, the expected responses should be verified for correctness the same logic simulation tool used to verify the functional correctness of the IC design.
The ATPG and BIST tools create a testbench to support this verification process. A testbench is a correction of input values (input vector) and expected output values (output vector). The testbench applies the generated input vectors to the circuit design (a simulation model of the circuit), and checks the responses. The testbench is simulated by a logic simulator, the results are compared with the expected values, and any mismatches discovered are corrected before finalizing the netlist of the design.
The Design for Testability (DFT) tools create two kinds of testbenches: parallel testbench and serial testbench. A parallel testbench involves setting the state of each memory element such as flip-flop or latch in a design before application of a test vector. This shortens verification time somewhat, but does not reflect the actual methodology used to test the IC in production. A serial testbench receives the test pattern only form the primary inputs of the design, and provides a complete and accurate simulation of the workings of the test circuitry.
A parallel testbench simulation takes a long time, for example, several hours to a day, or a day to several weeks, depending on the size of the design, the speed of the computers running the simulation, the speed of the simulator used, and the like. A serial testbench simulation takes even longer. Thus, since a full serial simulation is impractical, the current standard procedure is to simulate a few vectors to test the workings of the basic DFT logic, and then simulate the full vector set using parallel simulation. However, this verification procedure is still barely tolerable for ASIC designs, and the verification is a major bottleneck for microprocessor designs.
The long verification time imposes a significant burden on design schedule to achieve a required short time-to-market, whereas not performing the full verification process increases the risk of errors in the completed IC design. In addition, some designs are not amenable to parallel simulation, and some microprocessor designs cannot be verified using parallel testbenches because of the name space mismatch between the ATPG model and the golden simulation model. Furthermore, increasing IC sizes worsen the situation, since there are more vectors to verify, and more verification time per vector is required.